1. Field of the Invention
This invention relates generally to Electronic Design Automation (EDA) and, in particular, to automating pin assignments through an EDA development tool.
2. Description of the Related Art
In the field of electronics, various electronic design automation tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, EDA tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package. These tools commonly offer the designer the option of inputting the design in at least one high-level hardware description language (HDL).
As more and more functionality has been placed onto PLDs, the number of pins provided for communication between the PLD and external devices has drastically increased. The pin assignments for thousands of pins are still handled by a designer manually assigning the pins. That is, the design engineer will specify that the clock is to communicate with pin 1, address 1 is assigned to pin 2, address 2 is assigned to pin 3, and so on. A mistake in manually assigning the pins will cause the system to fail. Additionally, a design engineer may obtain hardware intellectual property (IP) that is placed into a system during design. While the IP provider verifies that the IP block is functional, they do not provide information on how the IP block wires out or any pin assignment information for placing the IP block on a particular printed circuit board. Consequently, the design engineer must manually assign the pins during the design process.
As a result, there is a need to solve the problems of the prior art to automate device pin assignments for the design of an integrated circuit.